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stm32 /stm32n6 /STM32N655 /SYSCFG /SYSCFG_NPU_ICNCR

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Interpret as SYSCFG_NPU_ICNCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)INTERLEAVING_ACTIVE

INTERLEAVING_ACTIVE=B_0x0

Description

SYSCFG NPU RAM interleaving control register

Fields

INTERLEAVING_ACTIVE

Control interleaving on NPU RAMs

0 (B_0x0): Interleaving disabled

1 (B_0x1): Interleaving enabled

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32