stm32 /stm32n6 /STM32N655 /TIM1 /TIM1_BDTR

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Interpret as TIM1_BDTR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DTG0 (B_0x0)LOCK 0 (B_0x0)OSSI 0 (B_0x0)OSSR 0 (B_0x0)BKE 0 (B_0x0)BKP 0 (B_0x0)AOE 0 (B_0x0)MOE 0 (B_0x0)BKF0 (B_0x0)BK2F0 (B_0x0)BK2E 0 (B_0x0)BK2P 0 (B_0x0)BKDSRM 0 (BK2DSRM)BK2DSRM 0 (B_0x0)BKBID 0 (BK2BID)BK2BID

BKE=B_0x0, OSSI=B_0x0, BKF=B_0x0, MOE=B_0x0, BK2F=B_0x0, BK2P=B_0x0, BKDSRM=B_0x0, BK2E=B_0x0, AOE=B_0x0, OSSR=B_0x0, BKBID=B_0x0, LOCK=B_0x0, BKP=B_0x0

Description

TIM1 break and dead-time register

Fields

DTG

Dead-time generator setup

LOCK

Lock configuration

0 (B_0x0): LOCK OFF - No bit is write protected.

1 (B_0x1): LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKBID/BK2BID/BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written.

2 (B_0x2): LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written.

3 (B_0x3): LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written.

OSSI

Off-state selection for idle mode

0 (B_0x0): When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO logic and which imposes a Hi-Z state).

1 (B_0x1): When inactive, OC/OCN outputs are first forced with their inactive level then forced to their idle level after the deadtime. The timer maintains its control over the output.

OSSR

Off-state selection for Run mode

0 (B_0x0): When inactive, OC/OCN outputs are disabled (the timer releases the output control which is taken over by the GPIO logic, which forces a Hi-Z state).

1 (B_0x1): When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 (the output is still controlled by the timer).

BKE

Break enable

0 (B_0x0): Break function disabled

1 (B_0x1): Break function enabled

BKP

Break polarity

0 (B_0x0): Break input tim_brk is active low

1 (B_0x1): Break input tim_brk is active high

AOE

Automatic output enable

0 (B_0x0): MOE can be set only by software

1 (B_0x1): MOE can be set by software or automatically at the next update event (if none of the break inputs tim_brk and tim_brk2 is active)

MOE

Main output enable

0 (B_0x0): In response to a break 2 event. OC and OCN outputs are disabled

1 (B_0x1): OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register).

BKF

Break filter

0 (B_0x0): No filter, tim_brk acts asynchronously

1 (B_0x1): fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2

2 (B_0x2): fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4

3 (B_0x3): fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8

4 (B_0x4): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6

5 (B_0x5): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8

6 (B_0x6): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6

7 (B_0x7): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8

8 (B_0x8): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6

9 (B_0x9): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8

10 (B_0xA): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5

11 (B_0xB): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6

12 (B_0xC): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8

13 (B_0xD): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5

14 (B_0xE): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6

15 (B_0xF): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8

BK2F

Break 2 filter

0 (B_0x0): No filter, tim_brk2 acts asynchronously

1 (B_0x1): fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2

2 (B_0x2): fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4

3 (B_0x3): fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8

4 (B_0x4): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6

5 (B_0x5): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8

6 (B_0x6): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6

7 (B_0x7): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8

8 (B_0x8): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6

9 (B_0x9): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8

10 (B_0xA): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5

11 (B_0xB): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6

12 (B_0xC): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8

13 (B_0xD): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5

14 (B_0xE): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6

15 (B_0xF): fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8

BK2E

Break 2 enable

0 (B_0x0): Break2 function disabled

1 (B_0x1): Break2 function enabled

BK2P

Break 2 polarity

0 (B_0x0): Break input tim_brk2 is active low

1 (B_0x1): Break input tim_brk2 is active high

BKDSRM

Break disarm

0 (B_0x0): Break input tim_brk is armed

1 (B_0x1): Break input tim_brk is disarmed

BK2DSRM

Break2 disarm

BKBID

Break bidirectional

0 (B_0x0): Break input tim_brk in input mode

1 (B_0x1): Break input tim_brk in bidirectional mode

BK2BID

Break2 bidirectional

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