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stm32 /stm32n6 /STM32N655 /TIM1 /TIM1_CCR5

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Interpret as TIM1_CCR5

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CCR50 (B_0x0)GC5C1 0 (B_0x0)GC5C2 0 (B_0x0)GC5C3

GC5C2=B_0x0, GC5C1=B_0x0, GC5C3=B_0x0

Description

TIM1 capture/compare register 5

Fields

CCR5

Capture/compare 5 value
GC5C1

Group channel 5 and channel 1

0 (B_0x0): No effect of oc5ref on oc1refc

1 (B_0x1): oc1refc is the logical AND of oc1ref and oc5ref
GC5C2

Group channel 5 and channel 2

0 (B_0x0): No effect of tim_oc5ref on tim_oc2refc

1 (B_0x1): tim_oc2refc is the logical AND of tim_oc2ref and tim_oc5ref
GC5C3

Group channel 5 and channel 3

0 (B_0x0): No effect of tim_oc5ref on tim_oc3refc

1 (B_0x1): tim_oc3refc is the logical AND of tim_oc3ref and tim_oc5ref

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32