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stm32 /stm32n6 /STM32N655 /TIM1 /TIM1_TISEL

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Interpret as TIM1_TISEL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)TI1SEL0 (B_0x0)TI2SEL0 (B_0x0)TI3SEL0 (B_0x0)TI4SEL

TI4SEL=B_0x0, TI2SEL=B_0x0, TI3SEL=B_0x0, TI1SEL=B_0x0

Description

TIM1 timer input selection register

Fields

TI1SEL

Selects tim_ti1[15:0] input

0 (B_0x0): tim_ti1_in0: TIMx_CH1

1 (B_0x1): tim_ti1_in1

15 (B_0xF): tim_ti1_in15
TI2SEL

Selects tim_ti2[15:0] input

0 (B_0x0): tim_ti2_in0: TIMx_CH2

1 (B_0x1): tim_ti2_in1

15 (B_0xF): tim_ti2_in15
TI3SEL

Selects tim_ti3[15:0] input

0 (B_0x0): tim_ti3_in0: TIMx_CH2

1 (B_0x1): tim_ti3_in1

15 (B_0xF): tim_ti3_in15
TI4SEL

Selects tim_ti4[15:0] input

0 (B_0x0): tim_ti4_in0: TIMx_CH4

1 (B_0x1): tim_ti4_in1

15 (B_0xF): tim_ti4_in15

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32