OC1M=B_0x0, OC1PE=B_0x0, CC1S=B_0x0, OC1FE=B_0x0
TIM14 capture/compare mode register 1 [alternate]
| CC1S | Capture/Compare 1 selection 0 (B_0x0): CC1 channel is configured as output. 1 (B_0x1): CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1. |
| OC1FE | Output compare 1 fast enable 0 (B_0x0): CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles. 1 (B_0x1): An active edge on the trigger input acts like a compare match on CC1 output. OC is then set to the compare level independently of the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if the channel is configured in PWM1 or PWM2 mode. |
| OC1PE | Output compare 1 preload enable 0 (B_0x0): Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. 1 (B_0x1): Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event. |
| OC1M | OC1M[2:0]: Output compare 1 mode (refer to bit 16 for OC1M[3]) 0 (B_0x0): Frozen. The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs. 1 (B_0x1): Set channel 1 to active level on match. tim_oc1ref signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 2 (B_0x2): Set channel 1 to inactive level on match. tim_oc1ref signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 3 (B_0x3): Toggle - tim_oc1ref toggles when TIMx_CNT = TIMx_CCR1. 4 (B_0x4): Force inactive level - tim_oc1ref is forced low. 5 (B_0x5): Force active level - tim_oc1ref is forced high. 6 (B_0x6): PWM mode 1 - Channel 1 is active as long as TIMx_CNT less than TIMx_CCR1 else inactive. 7 (B_0x7): PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT less than TIMx_CCR1 else active |
| OC1M_1 | OC1M[3] |