stm32 /stm32n6 /STM32N655 /TIM17 /TIM17_DTR2

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Interpret as TIM17_DTR2

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DTGF0 (B_0x0)DTAE 0 (B_0x0)DTPE

DTAE=B_0x0, DTPE=B_0x0

Description

TIM17 timer deadtime register 2

Fields

DTGF

Dead-time falling edge generator setup

DTAE

Deadtime asymmetric enable

0 (B_0x0): Deadtime on rising and falling edges are identical, and defined with DTG[7:0] register

1 (B_0x1): Deadtime on rising edge is defined with DTG[7:0] register and deadtime on falling edge is defined with DTGF[7:0] bits.

DTPE

Deadtime preload enable

0 (B_0x0): Deadtime value is not preloaded

1 (B_0x1): Deadtime value preload is enabled

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