TIM18_CR2

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Interpret as TIM18_CR2

MMS=B_0x0, ADSYNC=B_0x0

Description

TIM18 control register 2

Fields

MMS

Master mode selection

0 (B_0x0): Reset - the UG bit from the TIMx_EGR register is used as a trigger output (tim_trgo).

1 (B_0x1): Enable - the Counter enable signal, tim_cnt_en, is used as a trigger output (tim_trgo). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated when the CEN control bit is written.

2 (B_0x2): Update - The update event is selected as a trigger output (tim_trgo). For instance a master timer can then be used as a prescaler for a slave timer.

ADSYNC

ADC synchronization

0 (B_0x0): The timer operates independently from the ADC

1 (B_0x1): The timer operation is synchronized with the ADC clock to provide jitter-free sampling point. This mode can be enabled only with specific ADC / timer clock relationship. Refer to Section 48.3.8 for requirements.

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