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stm32 /stm32n6 /STM32N655 /TIM18 /TIM18_SR

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Interpret as TIM18_SR

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15 1211 87 43 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)UIF

UIF=B_0x0

Description

TIM18 status register

Fields

UIF

Update interrupt flag

0 (B_0x0): No update occurred.

1 (B_0x1): Update interrupt pending. This bit is set by hardware when the registers are updated:

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32