PHYCCSEL=B_0x0, TXMODE=B_0x0, ANAMODE=B_0x0, CC1TCDIS=B_0x0, RXMODE=B_0x0, CCENABLE=B_0x0, PHYRXEN=B_0x0, TXHRST=B_0x0, TXSEND=B_0x0, RDCH=B_0x0, CC2TCDIS=B_0x0, FRSTX=B_0x0
UCPD control register
| TXMODE | Type of Tx packet 0 (B_0x0): Transmission of Tx packet previously defined in other registers 1 (B_0x1): Cable Reset sequence 2 (B_0x2): BIST test sequence (BIST Carrier Mode 2) |
| TXSEND | Command to send a Tx packet 0 (B_0x0): No effect 1 (B_0x1): Start Tx packet transmission |
| TXHRST | Command to send a Tx Hard Reset 0 (B_0x0): No effect 1 (B_0x1): Start Tx Hard Reset message |
| RXMODE | Receiver mode 0 (B_0x0): Normal receive mode 1 (B_0x1): BIST receive mode (BIST test data mode) |
| PHYRXEN | USB Power Delivery receiver enable 0 (B_0x0): Disable 1 (B_0x1): Enable |
| PHYCCSEL | CC1/CC2 line selector for USB Power Delivery signaling 0 (B_0x0): Use CC1 IO for Power Delivery communication 1 (B_0x1): Use CC2 IO for Power Delivery communication |
| ANASUBMODE | Analog PHY sub-mode |
| ANAMODE | Analog PHY operating mode 0 (B_0x0): Source 1 (B_0x1): Sink |
| CCENABLE | CC line enable 0 (B_0x0): Disable both PHYs 1 (B_0x1): Enable CC1 PHY 2 (B_0x2): Enable CC2 PHY 3 (B_0x3): Enable CC1 and CC2 PHY |
| FRSRXEN | FRS event detection enable 1 (B_0x1): Enable |
| FRSTX | FRS Tx signaling enable. 0 (B_0x0): No effect 1 (B_0x1): Enable |
| RDCH | Rdch condition drive 0 (B_0x0): No effect 1 (B_0x1): Rdch condition drive |
| CC1TCDIS | CC1 Type-C detector disable 0 (B_0x0): Enable 1 (B_0x1): Disable |
| CC2TCDIS | CC2 Type-C detector disable 0 (B_0x0): Enable 1 (B_0x1): Disable |