SCEN=B_0x0, DEP=B_0x0, ONEBIT=B_0x0, HDSEL=B_0x0, DDRE=B_0x0, CTSE=B_0x0, RXFTCFG=B_0x0, OVRDIS=B_0x0, DMAR=B_0x0, IREN=B_0x0, WUS0=B_0x0, CTSIE=B_0x0, WUS1=B_0x0, RTSE=B_0x0, DMAT=B_0x0, TCBGTIE=B_0x0, IRLP=B_0x0, RXFTIE=B_0x0, TXFTIE=B_0x0, SCARCNT=B_0x0, NACK=B_0x0, WUFIE=B_0x0, DEM=B_0x0, EIE=B_0x0, TXFTCFG=B_0x0
USART control register 3
| EIE | Error interrupt enable 0 (B_0x0): Interrupt inhibited 1 (B_0x1): interrupt generated when FE=1 or ORE=1 or NE=1 or UDR = 1 (in SPI slave mode) in the USART_ISR register. |
| IREN | IrDA mode enable 0 (B_0x0): IrDA disabled 1 (B_0x1): IrDA enabled |
| IRLP | IrDA low-power 0 (B_0x0): Normal mode 1 (B_0x1): Low-power mode |
| HDSEL | Half-duplex selection 0 (B_0x0): Half-duplex mode is not selected 1 (B_0x1): Half-duplex mode is selected |
| NACK | Smartcard NACK enable 0 (B_0x0): NACK transmission in case of parity error is disabled 1 (B_0x1): NACK transmission during parity error is enabled |
| SCEN | Smartcard mode enable 0 (B_0x0): Smartcard mode disabled 1 (B_0x1): Smartcard mode enabled |
| DMAR | DMA enable receiver 0 (B_0x0): DMA mode is disabled for reception 1 (B_0x1): DMA mode is enabled for reception |
| DMAT | DMA enable transmitter 0 (B_0x0): DMA mode is disabled for transmission 1 (B_0x1): DMA mode is enabled for transmission |
| RTSE | RTS enable 0 (B_0x0): RTS hardware flow control disabled 1 (B_0x1): RTS output enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted. The RTS output is deasserted (pulled to 0) when data can be received. |
| CTSE | CTS enable 0 (B_0x0): CTS hardware flow control disabled 1 (B_0x1): CTS mode enabled, data is only transmitted when the CTS input is deasserted (tied to 0). If the CTS input is asserted while data is being transmitted, then the transmission is completed before stopping.If data is written into the data register while CTS is asserted, the transmission is postponed until CTS is deasserted. |
| CTSIE | CTS interrupt enable 0 (B_0x0): Interrupt is inhibited 1 (B_0x1): An interrupt is generated whenever CTSIF=1 in the USART_ISR register |
| ONEBIT | One sample bit method enable 0 (B_0x0): Three sample bit method 1 (B_0x1): One sample bit method |
| OVRDIS | Overrun Disable 0 (B_0x0): Overrun Error Flag, ORE, is set when received data is not read before receiving new data. 1 (B_0x1): Overrun functionality is disabled. If new data is received while the RXNE flag is still set |
| DDRE | DMA Disable on Reception Error 0 (B_0x0): DMA is not disabled in case of reception error. The corresponding error flag is set but RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not asserted, so the erroneous data is not transferred (no DMA request), but next correct received data is transferred. (used for Smartcard mode) 1 (B_0x1): DMA is disabled following a reception error. The corresponding error flag is set, as well as RXNE. The DMA request is masked until the error flag is cleared. This means that the software must first disable the DMA request (DMAR = 0) or clear RXNE(RXFNE is case FIFO mode is enabled) before clearing the error flag. |
| DEM | Driver enable mode 0 (B_0x0): DE function is disabled. 1 (B_0x1): DE function is enabled. The DE signal is output on the RTS pin. |
| DEP | Driver enable polarity selection 0 (B_0x0): DE signal is active high. 1 (B_0x1): DE signal is active low. |
| SCARCNT | Smartcard auto-retry count 0 (B_0x0): retransmission disabled - No automatic retransmission in Transmission mode. |
| WUS0 | Wakeup from low-power mode interrupt flag selection 0 (B_0x0): WUF active on address match (as defined by ADD[7:0] and ADDM7) |
| WUS1 | Wakeup from low-power mode interrupt flag selection 0 (B_0x0): WUF active on address match (as defined by ADD[7:0] and ADDM7) |
| WUFIE | Wakeup from low-power mode interrupt enable 0 (B_0x0): Interrupt inhibited 1 (B_0x1): USART interrupt generated whenever WUF=1 in the USART_ISR register |
| TXFTIE | TXFIFO threshold interrupt enable 0 (B_0x0): Interrupt inhibited 1 (B_0x1): USART interrupt generated when TXFIFO reaches the threshold programmed in TXFTCFG. |
| TCBGTIE | Transmission Complete before guard time, interrupt enable 0 (B_0x0): Interrupt inhibited 1 (B_0x1): USART interrupt generated whenever TCBGT=1 in the USART_ISR register |
| RXFTCFG | Receive FIFO threshold configuration 0 (B_0x0): Receive FIFO reaches 1/8 of its depth 1 (B_0x1): Receive FIFO reaches 1/4 of its depth 2 (B_0x2): Receive FIFO reaches 1/2 of its depth 3 (B_0x3): Receive FIFO reaches 3/4 of its depth 4 (B_0x4): Receive FIFO reaches 7/8 of its depth 5 (B_0x5): Receive FIFO becomes full |
| RXFTIE | RXFIFO threshold interrupt enable 0 (B_0x0): Interrupt inhibited 1 (B_0x1): USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG. |
| TXFTCFG | TXFIFO threshold configuration 0 (B_0x0): TXFIFO reaches 1/8 of its depth 1 (B_0x1): TXFIFO reaches 1/4 of its depth 2 (B_0x2): TXFIFO reaches 1/2 of its depth 3 (B_0x3): TXFIFO reaches 3/4 of its depth 4 (B_0x4): TXFIFO reaches 7/8 of its depth 5 (B_0x5): TXFIFO becomes empty |