CSHT=B_0x0, FRCK=B_0x0, MTYP=B_0x0, EXTENDMEM=B_0x0
XSPI device configuration register 1
| CKMODE | clock mode 0 |
| FRCK | Free running clock 0 (B_0x0): CLK is not free running. 1 (B_0x1): CLK is free running (always provided). |
| CSHT | Chip-select high time 0 (B_0x0): NCS stays high for at least 1 cycle between external device commands. 1 (B_0x1): NCS stays high for at least 2 cycles between external device commands. 63 (B_0x3F): NCS stays high for at least 64 cycles between external device commands. |
| DEVSIZE | Device size |
| EXTENDMEM | extended memory support 0 (B_0x0): NCS1 and NCS2 values depend from CSSEL bit in XSPI_CR (software controlled). 1 (B_0x1): NCS1 and NCS2 values depend from the address of transfer (hardware controlled). |
| MTYP | Memory type 0 (B_0x0): Micron mode, D0/D1 ordering in DTR 8-data-bit mode. Regular-command protocol in single-, dual-, quad-, and octal-SPI modes. 1 (B_0x1): Macronix mode, D1/D0 ordering in DTR 8-data-bit mode. Regular-command protocol in single-, dual-, quad-, and octal-SPI modes. 2 (B_0x2): Standard mode 3 (B_0x3): Macronix RAM mode, D1/D0 ordering in DTR 8-data-bit mode. Regular-command protocol in single-, dual-, quad-, and octal-SPI modes with dedicated address mapping. 4 (B_0x4): HyperBus memory mode, the protocol follows the HyperBusless thansup> less than/sup>specification. 8-data-bit DTR mode must be selected. 5 (B_0x5): HyperBus register mode, addressing register space. The memory-mapped accesses in this mode must be non-cacheable, or indirect read/write modes must be used. |