stm32 /stm32n6 /STM32N655 /XSPI1 /XSPI_WPTCR

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Interpret as XSPI_WPTCR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DCYC0 (B_0x0)DHQC 0 (B_0x0)SSHIFT

SSHIFT=B_0x0, DHQC=B_0x0

Description

XSPI wrap timing configuration register

Fields

DCYC

Number of dummy cycles

DHQC

Delay hold quarter cycle

0 (B_0x0): no quarter cycle delay

1 (B_0x1): quarter cycle delay inserted

SSHIFT

Sample shift

0 (B_0x0): no shift

1 (B_0x1): 1/2 cycle shift

Links

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