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stm32 /stm32n6 /STM32N657 /CSI /CSI_LMCFGR

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Interpret as CSI_LMCFGR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0LANENB 0DL0MAP 0DL1MAP

Description

CSI-2 Host lane merger configuration register

Fields

LANENB

Number of lanes

1 (B_0x1): 1 lane for the reception

2 (B_0x2): 2 lanes for the reception
DL0MAP

Physical mapping of logical data lane 0

1 (B_0x1): Physical data lane 0 connected to logical data lane 0

2 (B_0x2): Physical data lane 0 connected to logical data lane 1
DL1MAP

Physical mapping of logical data lane 1

1 (B_0x1): Physical data lane 1 connected to logical data lane 0

2 (B_0x2): Physical data lane 1 connected to logical data lane 1

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32