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stm32 /stm32n6 /STM32N657 /CSI /CSI_PMCR

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Interpret as CSI_PMCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)FRXMDL0 0 (B_0x0)FRXMDL1 0 (B_0x0)FTXSMDL0 0 (B_0x0)DTDL 0 (B_0x0)RTDL0 0 (TUESDL0)TUESDL0 0 (TUEXDL0)TUEXDL0

RTDL0=B_0x0, DTDL=B_0x0, FTXSMDL0=B_0x0, FRXMDL1=B_0x0, FRXMDL0=B_0x0

Description

CSI PHY mode control register

Fields

FRXMDL0

Force to Rx mode the data lane 0

0 (B_0x0): Disabled

1 (B_0x1): Enabled
FRXMDL1

Force to Rx mode the data lane 1

0 (B_0x0): Disabled

1 (B_0x1): Enabled
FTXSMDL0

Force to Tx Stop mode the data lane 0

0 (B_0x0): Disabled

1 (B_0x1): Enabled
DTDL

Disable turn-around data lane 0

0 (B_0x0): Disabled

1 (B_0x1): Enabled
RTDL0

Turn-around request data lane 0

0 (B_0x0): No request

1 (B_0x1): Request for turn-around for DL0
TUESDL0

Tx ULP escape-mode data lane 0
TUEXDL0

Tx ULP exit sequence data lane 0

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32