stm32 /stm32n6 /STM32N657 /DCMIPP /DCMIPP_P0IER

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Interpret as DCMIPP_P0IER

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)LINEIE 0 (B_0x0)FRAMEIE 0 (B_0x0)VSYNCIE 0 (B_0x0)LIMITIE 0 (B_0x0)OVRIE

FRAMEIE=B_0x0, OVRIE=B_0x0, LINEIE=B_0x0, LIMITIE=B_0x0, VSYNCIE=B_0x0

Description

DCMIPP Pipe0 interrupt enable register

Fields

LINEIE

Multi-line capture completed interrupt enable

0 (B_0x0): No interrupt generation when the line is received

1 (B_0x1): An interrupt is generated after the full capture of a group of lines (or last line reached)

FRAMEIE

Frame capture completed interrupt enable

0 (B_0x0): No interrupt generation

1 (B_0x1): An interrupt is generated after the full capture of a cropped frame

VSYNCIE

VSYNC interrupt enable

0 (B_0x0): No interrupt generation

1 (B_0x1): An interrupt is generated on each VSYNC (captured or not)

LIMITIE

Limit interrupt enable

0 (B_0x0): No interrupt generation when the limit is reached

1 (B_0x1): An interrupt is generated when the limit is reached

OVRIE

Overrun interrupt enable

0 (B_0x0): No interrupt generation

1 (B_0x1): An interrupt is generated if the AXI master is unable to transfer the last data before new data (32-bit) are received.

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