LMAWM=B_0x0, DBM=B_0x0, LINEMULT=B_0x0, LMAWE=B_0x0, SWAPRB=B_0x0, FORMAT=B_0x0
DCMIPP Pipe1 pixel packer configuration register
| FORMAT | Memory format 0 (B_0x0): RGB888 or YUV444 1-buffer 1 (B_0x1): RGB565 1-buffer 2 (B_0x2): ARGB8888 (with A = 0xFF) 3 (B_0x3): RGBA8888 (with A = 0xFF) 4 (B_0x4): monochrome Y8 or G8 1-buffer 5 (B_0x5): YUV444 1-buffer (32 bpp, FOURCC = AYUV, with A = 0xFF) 6 (B_0x6): YUV422 1-buffer (16 bpp, FOURCC = YUYV) 7 (B_0x7): YUV422 2-buffer (16 bpp, FOURCC = none) 8 (B_0x8): YUV420 2-buffer (12 bpp, FOURCC = NV21), NV12 available with SWAPRB = 1 9 (B_0x9): YUV420 3-buffer (12 bpp, FOURCC = YV12) 10 (B_0xA): YUV422 1-buffer (16 bpp, FOURCC = UYVY) |
| SWAPRB | Swaps R-vs-B components if RGB, and U-vs-V components if YUV 0 (B_0x0): No swap of R-vs-B (U-vs-V) 1 (B_0x1): Swap active |
| LINEMULT | Amount of capture completed lines for LINE Event and Interrupt 0 (B_0x0): Event after one line 1 (B_0x1): Event after two lines 2 (B_0x2): Event after four lines 3 (B_0x3): Event after eight lines 4 (B_0x4): Event after sixteen lines 5 (B_0x5): Event after 32 lines 6 (B_0x6): Event after 64 lines 7 (B_0x7): Event after 128 lines |
| DBM | Double buffer mode 0 (B_0x0): No double buffer mode activated. Pipe1 always drains out the pixels to memory address set by DCMIPP_P1PPM0AR1, and DCMIPP_P1PPM1AR1 as well as DCMIPP_P1PPM2AR1 in case of semi-planar or multi-planar buffer configuration 1 (B_0x1): Double buffer mode activated. Output pixels address location switches from DCMIPP_P1PPM0AR1 to DCMIPP_P1PPM0AR2 alternatively on each frame. For the semi- and multi-planar operations, the output pixels switches from/to DCMIPP_P1PPM1AR1 to/from DCMIPP_P1PPM1AR2. Memory buffer switches from/to DCMIPP_P1PPM2AR1 to/from DCMIPP_P1PPM2AR2 for multi-planar operations. |
| LMAWM | Line multi address wrapping modulo. 0 (B_0x0): Wraps address after every line 1 (B_0x1): Wraps address after two lines 2 (B_0x2): Wraps address after four lines 3 (B_0x3): Wraps address after eight lines 4 (B_0x4): Wraps address after sixteen lines 5 (B_0x5): Wraps address after 32 lines 6 (B_0x6): Wraps address after 64 lines 7 (B_0x7): Wraps address after 128 lines |
| LMAWE | Line multi address wrapping enable bit. 0 (B_0x0): Line multi address wrapping disabled. 1 (B_0x1): Line multi address wrapping enabled. |