stm32 /stm32n6 /STM32N657 /DMA2D /DMA2D_BGPFCCR

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Interpret as DMA2D_BGPFCCR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)CM0 (B_0x0)CCM 0 (START)START 0CS0 (B_0x0)AM0 (B_0x0)AI 0 (B_0x0)RBS 0ALPHA

CCM=B_0x0, RBS=B_0x0, AI=B_0x0, CM=B_0x0, AM=B_0x0

Description

DMA2D background PFC control register

Fields

CM

Color mode

0 (B_0x0): ARGB8888

1 (B_0x1): RGB888

2 (B_0x2): RGB565

3 (B_0x3): ARGB1555

4 (B_0x4): ARGB4444

5 (B_0x5): L8

6 (B_0x6): AL44

7 (B_0x7): AL88

8 (B_0x8): L4

9 (B_0x9): A8

10 (B_0xA): A4

CCM

CLUT color mode

0 (B_0x0): ARGB8888

1 (B_0x1): RGB888

START

Start

CS

CLUT size

AM

Alpha mode

0 (B_0x0): No modification of the foreground image alpha channel value

1 (B_0x1): Replace original background image alpha channel value by ALPHA[7: 0]

2 (B_0x2): Replace original background image alpha channel value by ALPHA[7:0] multiplied with original alpha channel value

AI

Alpha Inverted

0 (B_0x0): Regular alpha

1 (B_0x1): Inverted alpha

RBS

Red/Blue swap

0 (B_0x0): Regular mode (RGB or ARGB)

1 (B_0x1): Swap mode (BGR or ABGR)

ALPHA

Alpha value

Links

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