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stm32 /stm32n6 /STM32N657 /DTS /DTS_TSCCLKSYNTHR

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Interpret as DTS_TSCCLKSYNTHR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CLK_SYNTH_LO0CLK_SYNTH_HI0CLK_SYNTH_HOLD 0 (B_0x0)CLK_SYTH_EN

CLK_SYTH_EN=B_0x0

Description

DTS TSC clock synthesizer register

Fields

CLK_SYNTH_LO

Synthesized clk_ts low period
CLK_SYNTH_HI

Synthesized clk_ts high period
CLK_SYNTH_HOLD

SDA master-to-SDA slave output hold delay/SDA slave-to-SDA master input setup delay
CLK_SYTH_EN

Synthesized clk_ts enable bit

0 (B_0x0): Disabled

1 (B_0x1): Enabled

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32