stm32 /stm32n6 /STM32N657 /ETH /ETH_DMAA4DACR

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Interpret as ETH_DMAA4DACR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TDWC0TDWD 0RDRC

Description

AXI4 descriptor ACE control register

Fields

TDWC

Transmit DMA Write Descriptor Cache control

TDWD

Transmit DMA Write Descriptor Domain control

RDRC

Receive DMA Read Descriptor Cache control

Links

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