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stm32 /stm32n6 /STM32N657 /ETH /ETH_MACECR

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Interpret as ETH_MACECR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0GPSL0 (DCRCC)DCRCC 0 (SPEN)SPEN 0 (USP)USP 0 (EIPGEN)EIPGEN 0EIPG0 (APDIM)APDIM

Description

Extended operating mode configuration register

Fields

GPSL

Giant Packet Size Limit
DCRCC

Disable CRC Checking for Received Packets
SPEN

Slow Protocol Detection Enable
USP

Unicast Slow Protocol Packet Detect
EIPGEN

Extended Inter-Packet Gap Enable
EIPG

Extended Inter-Packet Gap
APDIM

ARP Packet Drop if IP Address Mismatch

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32