TRGTMODSEL1=B_0x0, MCGREN0=B_0x0, PPSCMD=B_0x0, MCGREN1=B_0x0, TRGTMODSEL0=B_0x0
PPS control register
| PPSCMD | Flexible PPS Output 0 (eth_ptp_pps_out) Control 0 (B_0x0): No Command 1 (B_0x1): START Single Pulse. 2 (B_0x2): START Pulse Train. 3 (B_0x3): Cancel START. 4 (B_0x4): STOP Pulse Train at time. 5 (B_0x5): STOP Pulse Train immediately. 6 (B_0x6): Cancel STOP Pulse train. |
| PPSEN0 | Flexible PPS Output 0 Mode Enable |
| TRGTMODSEL0 | Target Time Register Mode for PPS Output 0 0 (B_0x0): Target Time registers are programmed only for generating the interrupt event. 1 (B_0x1): Enables MCGR Interrupt whose status bit is indicated by TSTARGT0 bit in Timestamp status register (ETH_MACTSSR) register 2 (B_0x2): Target Time registers are programmed for generating the interrupt event and starting or stopping the PPS output 0 signal generation. 3 (B_0x3): Target Time registers are programmed only for starting or stopping the PPS output 0 signal generation. No interrupt is asserted. |
| MCGREN0 | MCGR Mode Enable for PPS Output 0 0 (B_0x0): PPS mode 1 (B_0x1): MCGR mode |
| PPSCMD1 | Flexible PPS Output 1 Control |
| TRGTMODSEL1 | Target Time Register Mode for PPS Output 1 0 (B_0x0): Target time registers are programmed only for generating the interrupt event. 1 (B_0x1): Enabled MCGR Interrupt whose status bit is indicated by TSTARGT1 bit in Timestamp status register (ETH_MACTSSR) register 2 (B_0x2): Target time registers are programmed for generating the interrupt event and starting or stopping the PPS output signal generation. 3 (B_0x3): Target time registers are programmed only for starting or stopping the PPS output signal generation. No interrupt is asserted. |
| MCGREN1 | MCGR Mode Enable for PPS Output 1 0 (B_0x0): PPS mode 1 (B_0x1): MCGR mode |
| TIMESEL | Time Select |