stm32 /stm32n6 /STM32N657 /ETH /ETH_MTLESTCR

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Interpret as ETH_MTLESTCR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)EEST 0 (SSWL)SSWL 0 (B_0x0)DDBF 0 (B_0x0)DFBS 0 (B_0x0)LCSE 0 (B_0x0)TILS0CTOV0PTOV

TILS=B_0x0, EEST=B_0x0, LCSE=B_0x0, DDBF=B_0x0, DFBS=B_0x0

Description

EST Control Register

Fields

EEST

Enable EST

0 (B_0x0): EST disabled

1 (B_0x1): EST enabled

SSWL

Switch to S/W owned list

DDBF

Do not Drop frames during Frame Size Error

0 (B_0x0): Drop

1 (B_0x1): Don’t drop

DFBS

Drop Frames causing Scheduling Error

0 (B_0x0): Don’t drop

1 (B_0x1): Drop

LCSE

Loop Count to report Scheduling Error

0 (B_0x0): 4 iterations

1 (B_0x1): 8 iterations

2 (B_0x2): 16 iterations

3 (B_0x3): 32 iterations

TILS

Time Interval Left Shift Amount

0 (B_0x0): No left shift needed (equal to x1ns)

1 (B_0x1): Left shift TI by 1 bit (equal to x2ns)

2 (B_0x2): Left shift TI by 2 bits (equal to x4ns)

4 (B_0x4): Left shift TI by 7 bits (equal to x128ns)

CTOV

Current Time Offset Value

PTOV

PTP Time Offset Value

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