TEST=B_0x0, ASM=B_0x0, PXHD=B_0x0, CSR=B_0x0, CCE=B_0x0, INIT=B_0x0, TXP=B_0x0, BRSE=B_0x0, MON=B_0x0, NISO=B_0x0, EFBI=B_0x0, FDOE=B_0x0, DAR=B_0x0, CSA=B_0x0
FDCAN CC control register
| INIT | Initialization 0 (B_0x0): Normal operation 1 (B_0x1): Initialization is started (while FDCAN_CCCR.INIT = 1 CCE bit is automatically cleared when INIT bit is cleared) |
| CCE | Configuration change enable 0 (B_0x0): The CPU has no write access to the protected configuration registers 1 (B_0x1): The CPU has write access to the protected configuration registers (while FDCAN_CCCR.INIT = 1 CCE bit is automatically cleared when INIT bit is cleared) |
| ASM | ASM restricted operation mode 0 (B_0x0): Normal CAN operation 1 (B_0x1): Restricted operation mode active |
| CSA | Clock stop acknowledge 0 (B_0x0): No clock stop acknowledged 1 (B_0x1): FDCAN may be set in power down by stopping APB clock and kernel clock |
| CSR | Clock stop request 0 (B_0x0): No clock stop is requested 1 (B_0x1): Clock stop requested. When clock stop is requested, first INIT and then CSA is set |
| MON | Bus monitoring mode 0 (B_0x0): Bus monitoring mode is disabled 1 (B_0x1): Bus monitoring mode is enabled |
| DAR | Disable automatic retransmission 0 (B_0x0): Automatic retransmission of messages not transmitted successfully enabled 1 (B_0x1): Automatic retransmission disabled |
| TEST | Test mode enable 0 (B_0x0): Normal operation, register TEST holds reset values 1 (B_0x1): Test mode, write access to register TEST enabled |
| FDOE | FD operation enable 0 (B_0x0): FD operation disabled 1 (B_0x1): FD operation enabled |
| BRSE | FDCAN bitrate switching 0 (B_0x0): Bitrate switching for transmissions disabled 1 (B_0x1): Bitrate switching for transmissions enabled |
| PXHD | Protocol exception handling disable 0 (B_0x0): Protocol exception handling enabled 1 (B_0x1): Protocol exception handling disabled |
| EFBI | Edge filtering during bus integration 0 (B_0x0): Edge filtering disabled 1 (B_0x1): Two consecutive dominant tq required to detect an edge for hard synchronization |
| TXP | If this bit is set, the FDCAN pauses for two CAN bit times before starting the next transmission after successfully transmitting a frame. 0 (B_0x0): Disabled 1 (B_0x1): Enabled |
| NISO | Non ISO operation 0 (B_0x0): CAN FD frame format according to ISO11898-1 1 (B_0x1): CAN FD frame format according to Bosch CAN FD Specification V1.0 |