stm32 /stm32n6 /STM32N657 /FDCAN1 /FDCAN_TTOCF

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as FDCAN_TTOCF

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)OM0 (B_0x0)GEN 0 (B_0x0)TM 0LDSDL0IRTO0 (B_0x0)EECS 0AWL0 (B_0x0)EGTF 0 (B_0x0)ECC 0 (B_0x0)EVTP

EECS=B_0x0, TM=B_0x0, OM=B_0x0, ECC=B_0x0, EVTP=B_0x0, EGTF=B_0x0, GEN=B_0x0

Description

FDCAN TT operation configuration register

Fields

OM

Operation mode.

0 (B_0x0): Event-driven CAN communication, default

1 (B_0x1): TTCAN level 1

2 (B_0x2): TTCAN level 2

3 (B_0x3): TTCAN level 0

GEN

Gap enable.

0 (B_0x0): Strictly time-triggered operation

1 (B_0x1): External event-synchronized time-triggered operation

TM

Time master.

0 (B_0x0): Time master function disabled

1 (B_0x1): Potential time master

LDSDL

LD of synchronization deviation limit.

IRTO

Initial reference trigger offset.

EECS

Enable external clock synchronization

0 (B_0x0): External clock synchronization in FDCAN level 0, 2 disabled

1 (B_0x1): External clock synchronization in FDCAN level 0, 2 enabled

AWL

Application watchdog limit.

EGTF

Enable global time filtering.

0 (B_0x0): Global time filtering in FDCAN level 0, 2 is disabled

1 (B_0x1): Global time filtering in FDCAN level 0, 2 is enabled

ECC

Enable clock calibration.

0 (B_0x0): Automatic clock calibration in FDCAN level 0, 2 is disabled

1 (B_0x1): Automatic clock calibration in FDCAN level 0, 2 is enabled

EVTP

Event trigger polarity.

0 (B_0x0): Rising edge trigger

1 (B_0x1): Falling edge trigger

Links

()