stm32 /stm32n6 /STM32N657 /FDCAN1 /FDCAN_TXBC

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as FDCAN_TXBC

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TBSA0 (B_0x0)NDTB0 (B_0x0)TFQS0 (B_0x0)TFQM

TFQS=B_0x0, NDTB=B_0x0, TFQM=B_0x0

Description

FDCAN Tx buffer configuration register

Fields

TBSA

Tx buffers start address

NDTB

Number of dedicated transmit buffers

0 (B_0x0): No dedicated Tx buffers

TFQS

Transmit FIFO/queue size

0 (B_0x0): No Tx FIFO/queue

TFQM

Tx FIFO/queue mode

0 (B_0x0): Tx FIFO operation

1 (B_0x1): Tx queue operation.

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