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stm32 /stm32n6 /STM32N657 /FMC1 /FMC_BCHIER

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Interpret as FMC_BCHIER

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)DUEIE 0 (B_0x0)DERIE 0 (B_0x0)DEFIE 0 (B_0x0)DSRIE 0 (B_0x0)EPBRIE

DUEIE=B_0x0, DEFIE=B_0x0, EPBRIE=B_0x0, DSRIE=B_0x0, DERIE=B_0x0

Description

FMC BCH interrupt enable register

Fields

DUEIE

Decoder Uncorrectable Errors Interrupt enable

0 (B_0x0): Decoder Uncorrectable Errors Interrupt disable

1 (B_0x1): Decoder Uncorrectable Errors Interrupt enable
DERIE

Decoder Error Ready Interrupt enable

0 (B_0x0): Decoder Error Ready Interrupt disable

1 (B_0x1): Decoder Error Ready Interrupt enable
DEFIE

Decoder Error Found Interrupt enable

0 (B_0x0): Decoder Error Found Interrupt disable

1 (B_0x1): Decoder Error Found Interrupt enable
DSRIE

Decoder Syndrome Ready Interrupt enable

0 (B_0x0): Decoder Syndrome Ready Interrupt disable

1 (B_0x1): Decoder Syndrome Ready Interrupt enable
EPBRIE

Decoder Parity Bits Ready Interrupt enable

0 (B_0x0): Decoder Parity Bits Ready Interrupt disable

1 (B_0x1): Decoder Parity Bits Ready Interrupt enable

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32