FMC_CSQCFGR3

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Interpret as FMC_CSQCFGR3

AC5T=B_0x0, RAC2T=B_0x0, AC3T=B_0x0, AC4T=B_0x0, SDT=B_0x0, AC1T=B_0x0, AC2T=B_0x0, SNBR=B_0x0, RAC1T=B_0x0

Description

FMC NAND sequencer configuration register 3

Fields

SNBR	Number of sectors to be read/written 0 (B_0x0): 1 sector 1 (B_0x1): 2 sectors 63 (B_0x3F): 16 sectors
AC1T	Address cycle 1 sequencer timings 0 (B_0x0): ADDC1 issued with the timings programmed in FMC_PMEM 1 (B_0x1): ADDC1 issued with the timings programmed in FMC_PATT
AC2T	Address cycle 2 sequencer timings 0 (B_0x0): ADDC2 issued with the timings programmed in FMC_PMEM 1 (B_0x1): ADDC2 issued with the timings programmed in FMC_PATT
AC3T	Address cycle 3 sequencer timings 0 (B_0x0): ADDC3 issued with the timings programmed in FMC_PMEM 1 (B_0x1): ADDC3 issued with the timings programmed in FMC_PATT
AC4T	Address cycle 4sequencer timings 0 (B_0x0): ADDC4 issued with the timings programmed in FMC_PMEM 1 (B_0x1): ADDC4 issued with the timings programmed in FMC_PATT
AC5T	Address cycle 5 sequencer timings 0 (B_0x0): ADDC5 issued with the timings programmed in FMC_PMEM 1 (B_0x1): ADDC5 issued with the timings programmed in FMC_PATT
SDT	Spare data transfer sequencer timings 0 (B_0x0): Spare data transfer issued with the timings programmed in FMC_PMEM 1 (B_0x1): Spare data transfer issued with the timings programmed in FMC_PATT
RAC1T	Random Address cycle 1 sequencer timings 0 (B_0x0): Random ADDC1 issued with the timings programmed in FMC_PMEM 1 (B_0x1): Random ADDC1 issued with the timings programmed in FMC_PATT
RAC2T	Random Address cycle 2 sequencer timings 0 (B_0x0): Random ADDC2 issued with the timings programmed in FMC_PMEM 1 (B_0x1): Random ADDC2 issued with the timings programmed in FMC_PATT

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