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stm32 /stm32n6 /STM32N657 /FMC1 /FMC_PATT

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Interpret as FMC_PATT

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)ATTSET0 (B_0x0)ATTWAIT0 (B_0x0)ATTHOLD0 (B_0x0)ATTHIZ

ATTHIZ=B_0x0, ATTHOLD=B_0x0, ATTWAIT=B_0x0, ATTSET=B_0x0

Description

FMC attribute memory space timing registers

Fields

ATTSET

Attribute memory setup time

0 (B_0x0): 1 * fmc_ker_ck cycle

1 (B_0x1): 2 * fmc_ker_ck cycle

255 (B_0xFF): 256 * fmc_ker_ck cycles.
ATTWAIT

Attribute memory wait time

0 (B_0x0): 1 * fmc_ker_ck cycle (+ wait cycle introduced by deassertion of NWAIT)

1 (B_0x1): 2 * fmc_ker_ck cycles (+ wait cycle introduced by deassertion of NWAIT)

255 (B_0xFF): 256 * fmc_ker_ck cycles (+ wait cycle introduced by deasserting NWAIT)
ATTHOLD

Attribute memory hold time

0 (B_0x0): 1 * fmc_ker_ck cycle

1 (B_0x1): 2 * fmc_ker_ck cycle

255 (B_0xFF): 256 * fmc_ker_ck cycles.
ATTHIZ

Attribute memory data bus Hi-Z time

0 (B_0x0): 1 * fmc_ker_ck cycle

1 (B_0x1): 2 * fmc_ker_ck cycle

255 (B_0xFF): 256 * fmc_ker_ck cycles

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32