SDINIT=B_0x0, NB=B_0x0, WP=B_0x0, NC=B_0x0, SDCLK=B_0x0, SDEN=B_0x0, NR=B_0x0, RPIPE=B_0x0, MWID=B_0x0
SDRAM control registers for SDRAM device 1
| NC | Number of column address bits 0 (B_0x0): 8 bits 1 (B_0x1): 9 bits 2 (B_0x2): 10 bits 3 (B_0x3): 11 bits. |
| NR | Number of row address bits 0 (B_0x0): 11 bit 1 (B_0x1): 12 bits 2 (B_0x2): 13 bits |
| MWID | Memory data bus width. 0 (B_0x0): 8 bits 1 (B_0x1): 16 bits 2 (B_0x2): 32 bits |
| NB | Number of banks 0 (B_0x0): Two banks 1 (B_0x1): Four banks |
| CAS | CAS Latency 1 (B_0x1): 1 cycle 2 (B_0x2): 2 cycles 3 (B_0x3): 3 cycles |
| WP | Write protection 0 (B_0x0): Write accesses allowed 1 (B_0x1): Write accesses ignored |
| SDCLK | SDRAM clock configuration 0 (B_0x0): SDCLK clock disabled 1 (B_0x1): SDCLK period = 1 * fmc_ker_ck period 2 (B_0x2): SDCLK period = 2 * fmc_ker_ck periods 3 (B_0x3): SDCLK period = 3 * fmc_ker_ck periods |
| RPIPE | Read pipe 0 (B_0x0): No fmc_ker_ck clock cycle delay (default value) 1 (B_0x1): One fmc_ker_ck clock cycle delay 2 (B_0x2): Two fmc_ker_ck clock cycle delay |
| SDEN | SDRAM device enable 0 (B_0x0): SDRAM disabled 1 (B_0x1): SDRAM device enabled |
| SDINIT | SDRAM device initialization 0 (B_0x0): Initialization is not complete, the AXI accesses are rejected and an AXI slave error is generated. 1 (B_0x1): Initialization is complete and the device is ready to be accessed |