FCCCS=B_0x0, FCS=B_0x0, LCCCS=B_0x0, LCCHRS=B_0x0, LCS=B_0x0, FCCFR=B_0x0, LCCFR=B_0x0, FCCHRS=B_0x0
GFXTIM clock generator configuration register
| LCS | line clock source 0 (B_0x0): line clock counter underflow 1 (B_0x1): frame clock counter underflow 2 (B_0x2): HSYNC rising edge 3 (B_0x3): HSYNC falling edge 4 (B_0x4): VSYNC rising edge 5 (B_0x5): VSYNC falling edge 6 (B_0x6): TE rising edge 7 (B_0x7): TE falling edge |
| LCCCS | line clock counter clock source 0 (B_0x0): line clock counter disabled 1 (B_0x1): system clock selected |
| LCCFR | line clock counter force reload 0 (B_0x0): no effect 1 (B_0x1): line clock counter reload forced |
| LCCHRS | line clock counter hardware reload source 0 (B_0x0): no hardware reload 1 (B_0x1): frame clock counter underflow 2 (B_0x2): HSYNC rising edge 3 (B_0x3): HSYNC falling edge 4 (B_0x4): VSYNC rising edge 5 (B_0x5): VSYNC falling edge 6 (B_0x6): TE rising edge 7 (B_0x7): TE falling edge |
| FCS | frame clock source 0 (B_0x0): line clock counter underflow 1 (B_0x1): frame clock counter underflow 2 (B_0x2): HSYNC rising edge 3 (B_0x3): HSYNC falling edge 4 (B_0x4): VSYNC rising edge 5 (B_0x5): VSYNC falling edge 6 (B_0x6): TE rising edge 7 (B_0x7): TE falling edge |
| FCCCS | frame clock counter clock source 0 (B_0x0): frame clock counter disabled 1 (B_0x1): line clock counter underflow 2 (B_0x2): HSYNC rising edge 3 (B_0x3): HSYNC falling edge 4 (B_0x4): VSYNC rising edge 5 (B_0x5): VSYNC falling edge 6 (B_0x6): TE rising edge 7 (B_0x7): TE falling edge |
| FCCFR | frame clock counter force reload 0 (B_0x0): No effect 1 (B_0x1): frame clock counter reload forced |
| FCCHRS | frame- -clock counter hardware reload source 0 (B_0x0): no hardware reload 1 (B_0x1): line- -clock counter underflow 2 (B_0x2): HSYNC rising edge 3 (B_0x3): HSYNC falling edge 4 (B_0x4): VSYNC rising edge 5 (B_0x5): VSYNC falling edge 6 (B_0x6): TE rising edge 7 (B_0x7): TE falling edge |