stm32 /stm32n6 /STM32N657 /GPDMA /GPDMA_SMISR

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Interpret as GPDMA_SMISR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)MIS0 0 (B_0x0)MIS1 0 (B_0x0)MIS2 0 (B_0x0)MIS3 0 (B_0x0)MIS4 0 (B_0x0)MIS5 0 (B_0x0)MIS6 0 (B_0x0)MIS7 0 (B_0x0)MIS8 0 (B_0x0)MIS9 0 (B_0x0)MIS10 0 (B_0x0)MIS11 0 (B_0x0)MIS12 0 (B_0x0)MIS13 0 (B_0x0)MIS14 0 (B_0x0)MIS15

MIS2=B_0x0, MIS7=B_0x0, MIS1=B_0x0, MIS13=B_0x0, MIS0=B_0x0, MIS3=B_0x0, MIS11=B_0x0, MIS8=B_0x0, MIS15=B_0x0, MIS5=B_0x0, MIS4=B_0x0, MIS10=B_0x0, MIS14=B_0x0, MIS9=B_0x0, MIS6=B_0x0, MIS12=B_0x0

Description

GPDMA secure masked interrupt status register

Fields

MIS0

masked interrupt status of the secure channel x

0 (B_0x0): no interrupt occurred on the secure channel x

1 (B_0x1): an interrupt occurred on the secure channel x

MIS1

masked interrupt status of the secure channel x

0 (B_0x0): no interrupt occurred on the secure channel x

1 (B_0x1): an interrupt occurred on the secure channel x

MIS2

masked interrupt status of the secure channel x

0 (B_0x0): no interrupt occurred on the secure channel x

1 (B_0x1): an interrupt occurred on the secure channel x

MIS3

masked interrupt status of the secure channel x

0 (B_0x0): no interrupt occurred on the secure channel x

1 (B_0x1): an interrupt occurred on the secure channel x

MIS4

masked interrupt status of the secure channel x

0 (B_0x0): no interrupt occurred on the secure channel x

1 (B_0x1): an interrupt occurred on the secure channel x

MIS5

masked interrupt status of the secure channel x

0 (B_0x0): no interrupt occurred on the secure channel x

1 (B_0x1): an interrupt occurred on the secure channel x

MIS6

masked interrupt status of the secure channel x

0 (B_0x0): no interrupt occurred on the secure channel x

1 (B_0x1): an interrupt occurred on the secure channel x

MIS7

masked interrupt status of the secure channel x

0 (B_0x0): no interrupt occurred on the secure channel x

1 (B_0x1): an interrupt occurred on the secure channel x

MIS8

masked interrupt status of the secure channel x

0 (B_0x0): no interrupt occurred on the secure channel x

1 (B_0x1): an interrupt occurred on the secure channel x

MIS9

masked interrupt status of the secure channel x

0 (B_0x0): no interrupt occurred on the secure channel x

1 (B_0x1): an interrupt occurred on the secure channel x

MIS10

masked interrupt status of the secure channel x

0 (B_0x0): no interrupt occurred on the secure channel x

1 (B_0x1): an interrupt occurred on the secure channel x

MIS11

masked interrupt status of the secure channel x

0 (B_0x0): no interrupt occurred on the secure channel x

1 (B_0x1): an interrupt occurred on the secure channel x

MIS12

masked interrupt status of the secure channel x

0 (B_0x0): no interrupt occurred on the secure channel x

1 (B_0x1): an interrupt occurred on the secure channel x

MIS13

masked interrupt status of the secure channel x

0 (B_0x0): no interrupt occurred on the secure channel x

1 (B_0x1): an interrupt occurred on the secure channel x

MIS14

masked interrupt status of the secure channel x

0 (B_0x0): no interrupt occurred on the secure channel x

1 (B_0x1): an interrupt occurred on the secure channel x

MIS15

masked interrupt status of the secure channel x

0 (B_0x0): no interrupt occurred on the secure channel x

1 (B_0x1): an interrupt occurred on the secure channel x

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