SWREQ=B_0x0, TCEM=B_0x0, DREQ=B_0x0, TRIGM=B_0x0, TRIGPOL=B_0x0, BREQ=B_0x0, PFREQ=B_0x0
HPDMA channel 3 transfer register 2
| REQSEL | hardware request selection |
| SWREQ | software request 0 (B_0x0): no software request. The selected hardware request REQSEL[7:0] is taken into account. 1 (B_0x1): software request for a memory-to-memory transfer. The default selected hardware request as per REQSEL[7:0] is ignored. |
| DREQ | destination hardware request 0 (B_0x0): selected hardware request driven by a source peripheral (request signal taken into account by the HPDMA transfer scheduler over the source/read port) 1 (B_0x1): selected hardware request driven by a destination peripheral (request signal taken into account by the HPDMA transfer scheduler over the destination/write port) |
| BREQ | Block hardware request 0 (B_0x0): the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level. 1 (B_0x1): the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level (see Section 15.3.4). |
| PFREQ | Hardware request in peripheral flow control mode 0 (B_0x0): the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in HPDMA control mode. The HPDMA is programmed with HPDMA_CxCBR1.BNDT[15:0] and this is internally used by the hardware for the block transfer completion. 1 (B_0x1): the selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode. The HPDMA block transfer can be early completed by the peripheral itself (see Section 15.3.5 for more details). |
| TRIGM | trigger mode 0 (B_0x0): at block level: the first burst read of each block transfer is conditioned by one hit trigger (channel x = 12 to 15, for each block if a 2D/repeated block is configured with HPDMA_CxBR1.BRC[10:0] different to 0). 1 (B_0x1): channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level, the 2 (B_0x2): at link level: a LLI link transfer is conditioned by one hit trigger. The LLI data transfer (if any) is not conditioned. 3 (B_0x3): at programmed burst level: If SWREQ = 1, each programmed burst read is conditioned by one hit trigger. If SWREQ = 0, each programmed burst that is requested by the selected peripheral, is conditioned by one hit trigger. |
| TRIGSEL | trigger event input selection |
| TRIGPOL | trigger event polarity 0 (B_0x0): no trigger (masked trigger event) 1 (B_0x1): trigger on the rising edge 2 (B_0x2): trigger on the falling edge 3 (B_0x3): same as 00 |
| TCEM | transfer complete event mode 0 (B_0x0): at block level (when HPDMA_CxBR1.BNDT[15:0] = 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. 1 (B_0x1): channel x = 0 to 11, same as 00; channel x=12 to 15, at 2D/repeated block level (when HPDMA_CxBR1.BRC[10:0] = 0 and HPDMA_CxBR1.BNDT[15:0] = 0), the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block. 2 (B_0x2): at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block transfer or a 2D/repeated block transfer for channel x = 12 to 15), if any data transfer. 3 (B_0x3): at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI updates the link address HPDMA_CxLLR.LA[15:2] to zero and clears all the HPDMA_CxLLR update bits (UT1, UT2, UB1, USA, UDA and ULL, plus UT3 and UB2 if present). If the channel transfer is continuous/infinite, no event is generated. |