stm32 /stm32n6 /STM32N657 /I3C1 /I3C_SER

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as I3C_SER

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)CODERR0 (B_0x0)PERR 0 (B_0x0)STALL 0 (B_0x0)DOVR 0 (B_0x0)COVR 0 (B_0x0)ANACK 0 (B_0x0)DNACK 0 (B_0x0)DERR

CODERR=B_0x0, DNACK=B_0x0, PERR=B_0x0, DERR=B_0x0, ANACK=B_0x0, DOVR=B_0x0, COVR=B_0x0, STALL=B_0x0

Description

I3C status error register

Fields

CODERR

Protocol error code/type

0 (B_0x0): CE0 error (transaction after sending CCC):

1 (B_0x1): CE1 error (monitoring error):

2 (B_0x2): CE2 error (no response to broadcast address):

3 (B_0x3): CE3 error (failed controller-role hand-off):

8 (B_0x8): TE0 error (invalid broadcast address 0b111_1110 + W):

9 (B_0x9): TE1 error (CCC code):

10 (B_0xA): TE2 error (write data):

11 (B_0xB): TE3 error (assigned address during dynamic address arbitration):

12 (B_0xC): TE4 error (0b111_1110 + R missing after Sr during dynamic address arbitration):

13 (B_0xD): TE5 error (transaction after detecting CCC):

14 (B_0xE): TE6 error (monitoring error):

PERR

Protocol error

0 (B_0x0): no detected error

1 (B_0x1): whatever controller or target, hardware detected a protocol error, as detailed in CODERR[3:0]

STALL

SCL stall error (when the I3C acts as target)

0 (B_0x0): no detected error

1 (B_0x1): target detected that SCL was stable for more than 125 s during an I3C SDR data read (during a direct CCC read, a private read, or an IB)

DOVR

RX-FIFO overrun or TX-FIFO underrun

0 (B_0x0): no detected error

1 (B_0x1): whatever controller or target, hardware detected either:

COVR

C-FIFO underrun or S-FIFO overrun (when the I3C acts as controller)

0 (B_0x0): no detected error

1 (B_0x1): controller detected either:

ANACK

Address not acknowledged (when the I3C is configured as controller)

0 (B_0x0): no detected error

1 (B_0x1): controller detected that the static/dynamic address was not acknowledged by a target, either during:

DNACK

Data not acknowledged (when the I3C acts as controller)

0 (B_0x0): no detected error

1 (B_0x1): controller detected that a data byte is not acknowledged by a target, either during:

DERR

Data error (when the I3C acts as controller)

0 (B_0x0): no detected error

1 (B_0x1): controller detected a data error during the controller-role hand-off procedure (GETACCCR CCC, formerly known as GETACCMST) when the received target address or/and the parity bit do no match. Active controller keeps controller-role.

Links

()