Regviz

stm32 /stm32n6 /STM32N657 /ICACHE /ICACHE_SR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as ICACHE_SR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32h5/STM32H523/ICACHE/ICACHE_SR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)BUSYF 0 (B_0x0)BSYENDF 0 (B_0x0)ERRF

BUSYF=B_0x0, ERRF=B_0x0, BSYENDF=B_0x0

Description

ICACHE status register

Fields

BUSYF

busy flag

0 (B_0x0): cache not busy on a CACHEINV operation

1 (B_0x1): cache executing a full invalidate CACHEINV operation
BSYENDF

busy end flag

0 (B_0x0): cache busy

1 (B_0x1): full invalidate CACHEINV operation finished
ERRF

cache error flag

0 (B_0x0): no error

1 (B_0x1): an error occurred during the operation (cacheable write)

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32