stm32 /stm32n6 /STM32N657 /LPTIM1 /LPTIM1_ISR_INPUT

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Interpret as LPTIM1_ISR_INPUT

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)CC1IF 0 (ARRM)ARRM 0 (EXTTRIG)EXTTRIG 0 (ARROK)ARROK 0 (UP)UP 0 (DOWN)DOWN 0 (UE)UE 0 (REPOK)REPOK 0 (B_0x0)CC2IF 0 (B_0x0)CC1OF 0 (B_0x0)CC2OF 0 (DIEROK)DIEROK

CC1IF=B_0x0, CC1OF=B_0x0, CC2IF=B_0x0, CC2OF=B_0x0

Description

LPTIM1 interrupt and status register [alternate]

Fields

CC1IF

capture 1 interrupt flag

0 (B_0x0): No input capture occurred

1 (B_0x1): The counter value has been captured in the LPTIM_CCR1 register. (An edge has been detected on IC1 which matches the selected polarity). The CC1IF flag is automatically cleared by hardware once the captured value is read (CPU or DMA).CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register.

ARRM

Autoreload match

EXTTRIG

External trigger edge event

ARROK

Autoreload register update OK

UP

Counter direction change down to up

DOWN

Counter direction change up to down

UE

LPTIM update event occurred

REPOK

Repetition register update OK

CC2IF

Capture 2 interrupt flag

0 (B_0x0): No input capture occurred

1 (B_0x1): The counter value has been captured in the LPTIM_CCR2 register. (An edge has been detected on IC2 which matches the selected polarity). The CC2IF flag is automatically cleared by hardware once the captured value is read (CPU or DMA). The CC2IF flag can be cleared by writing 1 to the CC2CF bit in the LPTIM_ICR register.

CC1OF

Capture 1 over-capture flag

0 (B_0x0): No over-capture has been detected.

1 (B_0x1): The counter value has been captured in LPTIM_CCR1 register while CC1IF flag was already set.

CC2OF

Capture 2 over-capture flag

0 (B_0x0): No over-capture has been detected.

1 (B_0x1): The counter value has been captured in LPTIM_CCR2 register while CC2IF flag was already set.

DIEROK

Interrupt enable register update OK

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