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stm32 /stm32n6 /STM32N657 /LPTIM5 /LPTIM5_CR

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Interpret as LPTIM5_CR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)ENABLE 0 (SNGSTRT)SNGSTRT 0 (CNTSTRT)CNTSTRT 0 (COUNTRST)COUNTRST 0 (RSTARE)RSTARE

ENABLE=B_0x0

Description

LPTIM5 control register

Fields

ENABLE

LPTIM enable

0 (B_0x0): LPTIM is disabled. Writing ‘0’ to the ENABLE bit resets all the DMA request signals (input capture and update event DMA requests).

1 (B_0x1): LPTIM is enabled
SNGSTRT

LPTIM start in Single mode
CNTSTRT

Timer start in Continuous mode
COUNTRST

Counter reset
RSTARE

Reset after read enable

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32