stm32 /stm32n6 /STM32N657 /OTG1 /OTG_GRSTCTL

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Interpret as OTG_GRSTCTL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CSRST)CSRST 0 (PSRST)PSRST 0 (FCRST)FCRST 0 (RXFFLSH)RXFFLSH 0 (TXFFLSH)TXFFLSH 0 (B_0x0_HOST_MODE)TXFNUM0 (DMAREQ)DMAREQ 0 (AHBIDL)AHBIDL

TXFNUM=B_0x0_HOST_MODE

Description

OTG reset register

Fields

CSRST

Core soft reset

PSRST

Partial soft reset

FCRST

Host frame counter reset

RXFFLSH

Rx FIFO flush

TXFFLSH

Tx FIFO flush

TXFNUM

Tx FIFO number

0 (B_0x0_HOST_MODE): Non-periodic Tx FIFO flush

1 (B_0x1_HOST_MODE): Periodic Tx FIFO flush

2 (B_0x2_DEVICE_MODE): Tx FIFO 2 flush

15 (B_0xF_DEVICE_MODE): Tx FIFO 15 flush

16 (B_0x10_HOST_MODE): Flush all the transmit FIFOs

DMAREQ

DMA request signal enabled

AHBIDL

AHB master idle

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