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stm32 /stm32n6 /STM32N657 /OTG1 /OTG_PCGCCTL1

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Interpret as OTG_PCGCCTL1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (GATEEN)GATEEN 0 (B_0x0)CNTGATECLK 0 (RAMGATEEN)RAMGATEEN

CNTGATECLK=B_0x0

Description

OTG power and clock gating control register 1

Fields

GATEEN

Enable active clock gating
CNTGATECLK

Counter for clock gating

0 (B_0x0): 64 clocks

1 (B_0x1): 128 clocks
RAMGATEEN

Enable RAM clock gating

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32