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stm32 /stm32n6 /STM32N657 /RAMCFG /RAMCFG_FLEXRAMCR

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Interpret as RAMCFG_FLEXRAMCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)SRAMER 0 (B_0x0)SRAMHWERDIS 0 (B_0x0)ITCMCFG 0 (B_0x0)DTCMCFG

DTCMCFG=B_0x0, SRAMHWERDIS=B_0x0, ITCMCFG=B_0x0, SRAMER=B_0x0

Description

RAMCFG FLEXRAM control register

Fields

SRAMER

SRAM erase

0 (B_0x0): No erase operation ongoing

1 (B_0x1): Erase operation ongoing
SRAMHWERDIS

SRAM hardware erase disable

0 (B_0x0): Erase operation done after a system reset

1 (B_0x1): No erase operation done after a system reset, only for the retention part of the FLEXMEM when it is used as AXI RAM
ITCMCFG

Configuration of the FLEXMEM I-TCM extension

0 (B_0x0): FLEXMEM I-TCM extension entirely allocated as AXI RAM

1 (B_0x1): First 64 Kbytes (and corresponding ECC) allocated as I-TCM, remaining part allocated as AXI RAM

2 (B_0x2): FLEXMEM I-TCM extension entirely allocated as AXI RAM
DTCMCFG

Configuration of the FLEXMEM D-TCM extension

0 (B_0x0): FLEXMEM D-TCM extension allocated as AXI RAM

1 (B_0x1): FLEXMEM D-TCM extension allocated as DTCM

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32