stm32 /stm32n6 /STM32N657 /RCC /RCC_AHB5ENCR

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Interpret as RCC_AHB5ENCR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (HPDMA1ENC)HPDMA1ENC 0 (DMA2DENC)DMA2DENC 0 (JPEGENC)JPEGENC 0 (FMCENC)FMCENC 0 (XSPI1ENC)XSPI1ENC 0 (PSSIENC)PSSIENC 0 (SDMMC2ENC)SDMMC2ENC 0 (SDMMC1ENC)SDMMC1ENC 0 (XSPI2ENC)XSPI2ENC 0 (XSPIMENC)XSPIMENC 0 (MCE1ENC)MCE1ENC 0 (MCE2ENC)MCE2ENC 0 (MCE3ENC)MCE3ENC 0 (XSPI3ENC)XSPI3ENC 0 (MCE4ENC)MCE4ENC 0 (GFXMMUENC)GFXMMUENC 0 (GPUENC)GPUENC 0 (ETH1MACENC)ETH1MACENC 0 (ETH1TXENC)ETH1TXENC 0 (ETH1RXENC)ETH1RXENC 0 (ETH1ENC)ETH1ENC 0 (OTG1ENC)OTG1ENC 0 (OTGPHY1ENC)OTGPHY1ENC 0 (OTGPHY2ENC)OTGPHY2ENC 0 (OTG2ENC)OTG2ENC 0 (NPUCACHEENC)NPUCACHEENC 0 (NPUENC)NPUENC

Description

RCC AHB5 enable register

Fields

HPDMA1ENC

HPDMA1 enable

DMA2DENC

DMA2D enable

JPEGENC

JPEG enable

FMCENC

FMC enable

XSPI1ENC

XSPI1 enable

PSSIENC

PSSI enable

SDMMC2ENC

SDMMC2 enable

SDMMC1ENC

SDMMC1 enable

XSPI2ENC

XSPI2 enable

XSPIMENC

XSPIM enable

MCE1ENC

MCE1 enable

MCE2ENC

MCE2 enable

MCE3ENC

MCE3 enable

XSPI3ENC

XSPI3 enable

MCE4ENC

MCE4 enable

GFXMMUENC

GFXMMU enable

GPUENC

GPU enable

ETH1MACENC

ETH1MAC enable

ETH1TXENC

ETH1TX enable

ETH1RXENC

ETH1RX enable

ETH1ENC

ETH1 enable

OTG1ENC

OTG1 enable

OTGPHY1ENC

OTGPHY1 enable

OTGPHY2ENC

OTGPHY2 enable

OTG2ENC

OTG2 enable

NPUCACHEENC

NPUCACHE enable

NPUENC

NPU enable

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