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stm32 /stm32n6 /STM32N657 /RCC /RCC_AHB5ENR

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Interpret as RCC_AHB5ENR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)HPDMA1EN 0 (B_0x0)DMA2DEN 0 (B_0x0)JPEGEN 0 (B_0x0)FMCEN 0 (B_0x0)XSPI1EN 0 (B_0x0)PSSIEN 0 (B_0x0)SDMMC2EN 0 (B_0x0)SDMMC1EN 0 (B_0x0)XSPI2EN 0 (B_0x0)XSPIMEN 0 (B_0x0)MCE1EN 0 (B_0x0)MCE2EN 0 (B_0x0)MCE3EN 0 (B_0x0)XSPI3EN 0 (B_0x0)MCE4EN 0 (B_0x0)GFXMMUEN 0 (B_0x0)GPUEN 0 (B_0x0)ETH1MACEN 0 (B_0x0)ETH1TXEN 0 (B_0x0)ETH1RXEN 0 (B_0x0)ETH1EN 0 (B_0x0)OTG1EN 0 (B_0x0)OTGPHY1EN 0 (B_0x0)OTGPHY2EN 0 (B_0x0)OTG2EN 0 (B_0x0)NPUCACHEEN 0 (B_0x0)NPUEN

GPUEN=B_0x0, ETH1TXEN=B_0x0, GFXMMUEN=B_0x0, XSPI2EN=B_0x0, OTG2EN=B_0x0, NPUEN=B_0x0, ETH1MACEN=B_0x0, MCE2EN=B_0x0, MCE3EN=B_0x0, OTGPHY2EN=B_0x0, OTGPHY1EN=B_0x0, SDMMC1EN=B_0x0, SDMMC2EN=B_0x0, NPUCACHEEN=B_0x0, JPEGEN=B_0x0, OTG1EN=B_0x0, ETH1RXEN=B_0x0, MCE4EN=B_0x0, XSPI3EN=B_0x0, MCE1EN=B_0x0, PSSIEN=B_0x0, FMCEN=B_0x0, ETH1EN=B_0x0, XSPIMEN=B_0x0, XSPI1EN=B_0x0, DMA2DEN=B_0x0, HPDMA1EN=B_0x0

Description

RCC AHB5 enable register

Fields

HPDMA1EN

HPDMA1 enable

0 (B_0x0): HPDMA1 is disabled (default after reset)

1 (B_0x1): HPDMA1 is enabled
DMA2DEN

DMA2D enable

0 (B_0x0): DMA2D is disabled (default after reset)

1 (B_0x1): DMA2D is enabled
JPEGEN

JPEG enable

0 (B_0x0): JPEG is disabled (default after reset)

1 (B_0x1): JPEG is enabled
FMCEN

FMC enable

0 (B_0x0): FMC is disabled (default after reset)

1 (B_0x1): FMC is enabled
XSPI1EN

XSPI1 enable

0 (B_0x0): XSPI1 is disabled (default after reset)

1 (B_0x1): XSPI1 is enabled
PSSIEN

PSSI enable

0 (B_0x0): PSSI is disabled (default after reset)

1 (B_0x1): PSSI is enabled
SDMMC2EN

SDMMC2 enable

0 (B_0x0): SDMMC2 is disabled (default after reset)

1 (B_0x1): SDMMC2 is enabled
SDMMC1EN

SDMMC1 enable

0 (B_0x0): SDMMC1 is disabled (default after reset)

1 (B_0x1): SDMMC1 is enabled
XSPI2EN

XSPI2 enable

0 (B_0x0): XSPI2 is disabled (default after reset)

1 (B_0x1): XSPI2 is enabled
XSPIMEN

XSPIM enable

0 (B_0x0): XSPIM is disabled (default after reset)

1 (B_0x1): XSPIM is enabled
MCE1EN

MCE1 enable

0 (B_0x0): MCE1 is disabled (default after reset)

1 (B_0x1): MCE1 is enabled
MCE2EN

MCE2 enable

0 (B_0x0): MCE2 is disabled (default after reset)

1 (B_0x1): MCE2 is enabled
MCE3EN

MCE3 enable

0 (B_0x0): MCE3 is disabled (default after reset)

1 (B_0x1): MCE3 is enabled
XSPI3EN

XSPI3 enable

0 (B_0x0): XSPI3 is disabled (default after reset)

1 (B_0x1): XSPI3 is enabled
MCE4EN

MCE4 enable

0 (B_0x0): MCE4 is disabled (default after reset)

1 (B_0x1): MCE4 is enabled
GFXMMUEN

GFXMMU enable

0 (B_0x0): GFXMMU is disabled (default after reset)

1 (B_0x1): GFXMMU is enabled
GPUEN

GPU enable

0 (B_0x0): GPU is disabled (default after reset)

1 (B_0x1): GPU is enabled
ETH1MACEN

ETH1MAC enable

0 (B_0x0): ETH1MAC is disabled (default after reset)

1 (B_0x1): ETH1MAC is enabled
ETH1TXEN

ETH1TX enable

0 (B_0x0): ETH1TX is disabled (default after reset)

1 (B_0x1): ETH1TX is enabled
ETH1RXEN

ETH1RX enable

0 (B_0x0): ETH1RX is disabled (default after reset)

1 (B_0x1): ETH1RX is enabled
ETH1EN

ETH1 enable

0 (B_0x0): ETH1 is disabled (default after reset)

1 (B_0x1): ETH1 is enabled
OTG1EN

OTG1 enable

0 (B_0x0): OTG1 is disabled (default after reset)

1 (B_0x1): OTG1 is enabled
OTGPHY1EN

OTGPHY1 enable

0 (B_0x0): OTGPHY1 is disabled (default after reset)

1 (B_0x1): OTGPHY1 is enabled
OTGPHY2EN

OTGPHY2 enable

0 (B_0x0): OTGPHY2 is disabled (default after reset)

1 (B_0x1): OTGPHY2 is enabled
OTG2EN

OTG2 enable

0 (B_0x0): OTG2 is disabled (default after reset)

1 (B_0x1): OTG2 is enabled
NPUCACHEEN

NPUCACHE enable

0 (B_0x0): NPUCACHE is disabled (default after reset)

1 (B_0x1): NPUCACHE is enabled
NPUEN

NPU enable

0 (B_0x0): NPU is disabled (default after reset)

1 (B_0x1): NPU is enabled

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32