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stm32 /stm32n6 /STM32N657 /RCC /RCC_APB4LLPENCR

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Interpret as RCC_APB4LLPENCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (HDPLPENC)HDPLPENC 0 (LPUART1LPENC)LPUART1LPENC 0 (SPI6LPENC)SPI6LPENC 0 (I2C4LPENC)I2C4LPENC 0 (LPTIM2LPENC)LPTIM2LPENC 0 (LPTIM3LPENC)LPTIM3LPENC 0 (LPTIM4LPENC)LPTIM4LPENC 0 (LPTIM5LPENC)LPTIM5LPENC 0 (VREFBUFLPENC)VREFBUFLPENC 0 (RTCLPENC)RTCLPENC 0 (RTCAPBLPENC)RTCAPBLPENC 0 (R2GRETLPENC)R2GRETLPENC 0 (R2GNPULPENC)R2GNPULPENC 0 (SERFLPENC)SERFLPENC

Description

RCC APB4L Sleep enable register

Fields

HDPLPENC

HDP sleep enable
LPUART1LPENC

LPUART1 sleep enable
SPI6LPENC

SPI6 sleep enable
I2C4LPENC

I2C4 sleep enable
LPTIM2LPENC

LPTIM2 sleep enable
LPTIM3LPENC

LPTIM3 sleep enable
LPTIM4LPENC

LPTIM4 sleep enable
LPTIM5LPENC

LPTIM5 sleep enable
VREFBUFLPENC

VREFBUF sleep enable
RTCLPENC

RTC sleep enable
RTCAPBLPENC

RTCAPB sleep enable
R2GRETLPENC

R2GRET sleep enable
R2GNPULPENC

R2GNPU sleep enable
SERFLPENC

SERF sleep enable

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32