Regviz

stm32 /stm32n6 /STM32N657 /RCC /RCC_APB4LRSTCR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as RCC_APB4LRSTCR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/stm32/stm32n6/STM32N645/RCC/RCC_APB4LRSTCR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (HDPRSTC)HDPRSTC 0 (LPUART1RSTC)LPUART1RSTC 0 (SPI6RSTC)SPI6RSTC 0 (I2C4RSTC)I2C4RSTC 0 (LPTIM2RSTC)LPTIM2RSTC 0 (LPTIM3RSTC)LPTIM3RSTC 0 (LPTIM4RSTC)LPTIM4RSTC 0 (LPTIM5RSTC)LPTIM5RSTC 0 (VREFBUFRSTC)VREFBUFRSTC 0 (RTCRSTC)RTCRSTC 0 (R2GRETRSTC)R2GRETRSTC 0 (R2GNPURSTC)R2GNPURSTC 0 (SERFRSTC)SERFRSTC

Description

RCC APB4L reset register

Fields

HDPRSTC

HDP reset
LPUART1RSTC

LPUART1 reset
SPI6RSTC

SPI6 reset
I2C4RSTC

I2C4 reset
LPTIM2RSTC

LPTIM2 reset
LPTIM3RSTC

LPTIM3 reset
LPTIM4RSTC

LPTIM4 reset
LPTIM5RSTC

LPTIM5 reset
VREFBUFRSTC

VREFBUF reset
RTCRSTC

RTC reset
R2GRETRSTC

R2GRET reset
R2GNPURSTC

R2GNPU reset
SERFRSTC

SERF reset

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32