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stm32 /stm32n6 /STM32N657 /RCC /RCC_CFGR2

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Interpret as RCC_CFGR2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)PPRE10 (B_0x0)PPRE20 (B_0x0)PPRE40 (B_0x0)PPRE50 (B_0x0)HPRE0 (B_0x0)TIMPRE

PPRE1=B_0x0, PPRE4=B_0x0, HPRE=B_0x0, PPRE5=B_0x0, TIMPRE=B_0x0, PPRE2=B_0x0

Description

RCC configuration register 2

Fields

PPRE1

CPU domain APB1 prescaler

0 (B_0x0): rcc_pclk1 = sys_bus2_ck (default after reset)

1 (B_0x1): rcc_pclk1 = sys_bus2_ck / 2

2 (B_0x2): rcc_pclk1 = sys_bus2_ck / 4

3 (B_0x3): rcc_pclk1 = sys_bus2_ck / 8

4 (B_0x4): rcc_pclk1 = sys_bus2_ck / 16

5 (B_0x5): rcc_pclk1 = sys_bus2_ck / 32

6 (B_0x6): rcc_pclk1 = sys_bus2_ck / 64

7 (B_0x7): rcc_pclk1 = sys_bus2_ck / 128
PPRE2

CPU domain APB2 prescaler

0 (B_0x0): rcc_pclk2 = sys_bus2_ck (default after reset)

1 (B_0x1): rcc_pclk2 = sys_bus2_ck / 2

2 (B_0x2): rcc_pclk1 = sys_bus2_ck / 4

3 (B_0x3): rcc_pclk1 = sys_bus2_ck / 8

4 (B_0x4): rcc_pclk1 = sys_bus2_ck / 16

5 (B_0x5): rcc_pclk1 = sys_bus2_ck / 32

6 (B_0x6): rcc_pclk1 = sys_bus2_ck / 64

7 (B_0x7): rcc_pclk1 = sys_bus2_ck / 128
PPRE4

CPU domain APB4 prescaler

0 (B_0x0): rcc_pclk4 = sys_bus2_ck (default after reset)

1 (B_0x1): rcc_pclk4 = sys_bus2_ck / 2

2 (B_0x2): rcc_pclk1 = sys_bus2_ck / 4

3 (B_0x3): rcc_pclk1 = sys_bus2_ck / 8

4 (B_0x4): rcc_pclk1 = sys_bus2_ck / 16

5 (B_0x5): rcc_pclk1 = sys_bus2_ck / 32

6 (B_0x6): rcc_pclk1 = sys_bus2_ck / 64

7 (B_0x7): rcc_pclk1 = sys_bus2_ck / 128
PPRE5

CPU domain APB5 prescaler

0 (B_0x0): rcc_pclk5 = sys_bus2_ck (default after reset)

1 (B_0x1): rcc_pclk5 = sys_bus2_ck / 2

2 (B_0x2): rcc_pclk1 = sys_bus2_ck / 4

3 (B_0x3): rcc_pclk1 = sys_bus2_ck / 8

4 (B_0x4): rcc_pclk1 = sys_bus2_ck / 16

5 (B_0x5): rcc_pclk1 = sys_bus2_ck / 32

6 (B_0x6): rcc_pclk1 = sys_bus2_ck / 64

7 (B_0x7): rcc_pclk1 = sys_bus2_ck / 128
HPRE

AHB clock prescaler

0 (B_0x0): sys_bus2_ck= sys_bus_ck

1 (B_0x1): sys_bus2_ck = sys_bus_ck / 2 (default after reset)

2 (B_0x2): sys_bus2_ck= sys_bus_ck / 4

3 (B_0x3): sys_bus2_ck = sys_bus_ck / 8

4 (B_0x4): sys_bus2_ck = sys_bus_ck / 16

5 (B_0x5): sys_bus2_ck = sys_bus_ck / 32

6 (B_0x6): sys_bus2_ck = sys_bus_ck / 64

7 (B_0x7): sys_bus2_ck = sys_bus_ck / 128
TIMPRE

Timers clocks prescaler selection

0 (B_0x0): timg_ck = sys_bus_ck (default after reset)

1 (B_0x1): timg_ck = sys_bus_ck / 2

2 (B_0x2): timg_ck = sys_bus_ck / 4

Links

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Register Reference

https://github.com/modm-io/cmsis-svd-stm32