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stm32 /stm32n6 /STM32N657 /RCC /RCC_HSICFGR

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Interpret as RCC_HSICFGR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)HSIDIV 0 (B_0x0)HSITRIM0HSICAL

HSITRIM=B_0x0, HSIDIV=B_0x0

Description

RCC HSI configuration register

Fields

HSIDIV

HSI clock divider

0 (B_0x0): hsi_ck = hsi_osc_ck (default after reset)

1 (B_0x1): hsi_ck = hsi_osc_ck / 2
HSITRIM

HSI clock trimming

0 (B_0x0): bsec_hsi_cal[8:0] (default after reset)

62 (B_0x3E): bsec_hsi_cal[8:0] + 62

63 (B_0x3F): bsec_hsi_cal[8:0] + 63

64 (B_0x40): bsec_hsi_cal[8:0] - 64

65 (B_0x41): bsec_hsi_cal[8:0] - 63
HSICAL

HSI clock calibration

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32