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stm32 /stm32n6 /STM32N657 /RCC /RCC_MISCENSR

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Interpret as RCC_MISCENSR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DBGENS)DBGENS 0 (MCO1ENS)MCO1ENS 0 (MCO2ENS)MCO2ENS 0 (XSPIPHYCOMPENS)XSPIPHYCOMPENS 0 (PERENS)PERENS

Description

RCC miscellaneous enable register

Fields

DBGENS

DBG enable
MCO1ENS

MCO1 enable
MCO2ENS

MCO2 enable
XSPIPHYCOMPENS

XSPIPHYCOMP enable
PERENS

PER enable

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32