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stm32 /stm32n6 /STM32N657 /RCC /RCC_MISCLPENR

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Interpret as RCC_MISCLPENR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)DBGLPEN 0 (B_0x0)XSPIPHYCOMPLPEN 0 (B_0x0)PERLPEN

DBGLPEN=B_0x0, PERLPEN=B_0x0, XSPIPHYCOMPLPEN=B_0x0

Description

RCC miscellaneous configurations Sleep enable register

Fields

DBGLPEN

DBG sleep enable

0 (B_0x0): DBG is disabled in Sleep mode (default after reset)

1 (B_0x1): DBG is enabled in Sleep mode
XSPIPHYCOMPLPEN

XSPIPHYCOMP sleep enable

0 (B_0x0): XSPIPHYCOMP is disabled in Sleep mode (default after reset)

1 (B_0x1): XSPIPHYCOMP is enabled in Sleep mode
PERLPEN

PER sleep enable

0 (B_0x0): PER is disabled in Sleep mode (default after reset)

1 (B_0x1): PER is enabled in Sleep mode

Links

()

Register Reference

https://github.com/modm-io/cmsis-svd-stm32