stm32 /stm32n6 /STM32N657 /RIFSC /RIFSC_PPSR0

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Interpret as RIFSC_PPSR0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (B_0x0)PPEN0 0 (B_0x0)PPEN1 0 (B_0x0)PPEN2 0 (B_0x0)PPEN3 0 (B_0x0)PPEN4 0 (B_0x0)PPEN5 0 (B_0x0)PPEN6 0 (B_0x0)PPEN7 0 (B_0x0)PPEN8 0 (B_0x0)PPEN9 0 (B_0x0)PPEN10 0 (B_0x0)PPEN11 0 (B_0x0)PPEN12 0 (B_0x0)PPEN13 0 (B_0x0)PPEN14 0 (B_0x0)PPEN15 0 (B_0x0)PPEN16 0 (B_0x0)PPEN17 0 (B_0x0)PPEN18 0 (B_0x0)PPEN19 0 (B_0x0)PPEN20 0 (B_0x0)PPEN21 0 (B_0x0)PPEN22 0 (B_0x0)PPEN23 0 (B_0x0)PPEN24 0 (B_0x0)PPEN25 0 (B_0x0)PPEN26 0 (B_0x0)PPEN27 0 (B_0x0)PPEN28 0 (B_0x0)PPEN29 0 (B_0x0)PPEN30 0 (B_0x0)PPEN31

PPEN1=B_0x0, PPEN6=B_0x0, PPEN21=B_0x0, PPEN5=B_0x0, PPEN20=B_0x0, PPEN26=B_0x0, PPEN28=B_0x0, PPEN9=B_0x0, PPEN29=B_0x0, PPEN17=B_0x0, PPEN25=B_0x0, PPEN3=B_0x0, PPEN19=B_0x0, PPEN8=B_0x0, PPEN10=B_0x0, PPEN31=B_0x0, PPEN0=B_0x0, PPEN7=B_0x0, PPEN22=B_0x0, PPEN23=B_0x0, PPEN15=B_0x0, PPEN14=B_0x0, PPEN4=B_0x0, PPEN18=B_0x0, PPEN12=B_0x0, PPEN13=B_0x0, PPEN11=B_0x0, PPEN24=B_0x0, PPEN2=B_0x0, PPEN16=B_0x0, PPEN30=B_0x0, PPEN27=B_0x0

Description

RIFSC peripheral protection status register 0

Fields

PPEN0

peripheral protection enable 0

0 (B_0x0): SEC0, PRIV0, and RLOCK0 register bit not present.

1 (B_0x1): SEC0, PRIV0, and RLOCK0 register bit present.

PPEN1

peripheral protection enable 1

0 (B_0x0): SEC1, PRIV1, and RLOCK1 register bit not present.

1 (B_0x1): SEC1, PRIV1, and RLOCK1 register bit present.

PPEN2

peripheral protection enable 2

0 (B_0x0): SEC2, PRIV2, and RLOCK2 register bit not present.

1 (B_0x1): SEC2, PRIV2, and RLOCK2 register bit present.

PPEN3

peripheral protection enable 3

0 (B_0x0): SEC3, PRIV3, and RLOCK3 register bit not present.

1 (B_0x1): SEC3, PRIV3, and RLOCK3 register bit present.

PPEN4

peripheral protection enable 4

0 (B_0x0): SEC4, PRIV4, and RLOCK4 register bit not present.

1 (B_0x1): SEC4, PRIV4, and RLOCK4 register bit present.

PPEN5

peripheral protection enable 5

0 (B_0x0): SEC5, PRIV5, and RLOCK5 register bit not present.

1 (B_0x1): SEC5, PRIV5, and RLOCK5 register bit present.

PPEN6

peripheral protection enable 6

0 (B_0x0): SEC6, PRIV6, and RLOCK6 register bit not present.

1 (B_0x1): SEC6, PRIV6, and RLOCK6 register bit present.

PPEN7

peripheral protection enable 7

0 (B_0x0): SEC7, PRIV7, and RLOCK7 register bit not present.

1 (B_0x1): SEC7, PRIV7, and RLOCK7 register bit present.

PPEN8

peripheral protection enable 8

0 (B_0x0): SEC8, PRIV8, and RLOCK8 register bit not present.

1 (B_0x1): SEC8, PRIV8, and RLOCK8 register bit present.

PPEN9

peripheral protection enable 9

0 (B_0x0): SEC9, PRIV9, and RLOCK9 register bit not present.

1 (B_0x1): SEC9, PRIV9, and RLOCK9 register bit present.

PPEN10

peripheral protection enable 10

0 (B_0x0): SEC10, PRIV10, and RLOCK10 register bit not present.

1 (B_0x1): SEC10, PRIV10, and RLOCK10 register bit present.

PPEN11

peripheral protection enable 11

0 (B_0x0): SEC11, PRIV11, and RLOCK11 register bit not present.

1 (B_0x1): SEC11, PRIV11, and RLOCK11 register bit present.

PPEN12

peripheral protection enable 12

0 (B_0x0): SEC12, PRIV12, and RLOCK12 register bit not present.

1 (B_0x1): SEC12, PRIV12, and RLOCK12 register bit present.

PPEN13

peripheral protection enable 13

0 (B_0x0): SEC13, PRIV13, and RLOCK13 register bit not present.

1 (B_0x1): SEC13, PRIV13, and RLOCK13 register bit present.

PPEN14

peripheral protection enable 14

0 (B_0x0): SEC14, PRIV14, and RLOCK14 register bit not present.

1 (B_0x1): SEC14, PRIV14, and RLOCK14 register bit present.

PPEN15

peripheral protection enable 15

0 (B_0x0): SEC15, PRIV15, and RLOCK15 register bit not present.

1 (B_0x1): SEC15, PRIV15, and RLOCK15 register bit present.

PPEN16

peripheral protection enable 16

0 (B_0x0): SEC16, PRIV16, and RLOCK16 register bit not present.

1 (B_0x1): SEC16, PRIV16, and RLOCK16 register bit present.

PPEN17

peripheral protection enable 17

0 (B_0x0): SEC17, PRIV17, and RLOCK17 register bit not present.

1 (B_0x1): SEC17, PRIV17, and RLOCK17 register bit present.

PPEN18

peripheral protection enable 18

0 (B_0x0): SEC18, PRIV18, and RLOCK18 register bit not present.

1 (B_0x1): SEC18, PRIV18, and RLOCK18 register bit present.

PPEN19

peripheral protection enable 19

0 (B_0x0): SEC19, PRIV19, and RLOCK19 register bit not present.

1 (B_0x1): SEC19, PRIV19, and RLOCK19 register bit present.

PPEN20

peripheral protection enable 20

0 (B_0x0): SEC20, PRIV20, and RLOCK20 register bit not present.

1 (B_0x1): SEC20, PRIV20, and RLOCK20 register bit present.

PPEN21

peripheral protection enable 21

0 (B_0x0): SEC21, PRIV21, and RLOCK21 register bit not present.

1 (B_0x1): SEC21, PRIV21, and RLOCK21 register bit present.

PPEN22

peripheral protection enable 22

0 (B_0x0): SEC22, PRIV22, and RLOCK22 register bit not present.

1 (B_0x1): SEC22, PRIV22, and RLOCK22 register bit present.

PPEN23

peripheral protection enable 23

0 (B_0x0): SEC23, PRIV23, and RLOCK23 register bit not present.

1 (B_0x1): SEC23, PRIV23, and RLOCK23 register bit present.

PPEN24

peripheral protection enable 24

0 (B_0x0): SEC24, PRIV24, and RLOCK24 register bit not present.

1 (B_0x1): SEC24, PRIV24, and RLOCK24 register bit present.

PPEN25

peripheral protection enable 25

0 (B_0x0): SEC25, PRIV25, and RLOCK25 register bit not present.

1 (B_0x1): SEC25, PRIV25, and RLOCK25 register bit present.

PPEN26

peripheral protection enable 26

0 (B_0x0): SEC26, PRIV26, and RLOCK26 register bit not present.

1 (B_0x1): SEC26, PRIV26, and RLOCK26 register bit present.

PPEN27

peripheral protection enable 27

0 (B_0x0): SEC27, PRIV27, and RLOCK27 register bit not present.

1 (B_0x1): SEC27, PRIV27, and RLOCK27 register bit present.

PPEN28

peripheral protection enable 28

0 (B_0x0): SEC28, PRIV28, and RLOCK28 register bit not present.

1 (B_0x1): SEC28, PRIV28, and RLOCK28 register bit present.

PPEN29

peripheral protection enable 29

0 (B_0x0): SEC29, PRIV29, and RLOCK29 register bit not present.

1 (B_0x1): SEC29, PRIV29, and RLOCK29 register bit present.

PPEN30

peripheral protection enable 30

0 (B_0x0): SEC30, PRIV30, and RLOCK30 register bit not present.

1 (B_0x1): SEC30, PRIV30, and RLOCK30 register bit present.

PPEN31

peripheral protection enable 31

0 (B_0x0): SEC31, PRIV31, and RLOCK31 register bit not present.

1 (B_0x1): SEC31, PRIV31, and RLOCK31 register bit present.

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