ODD=B_0x0, DATFMT=B_0x0, I2SMOD=B_0x0, I2SCFG=B_0x0, FIXCH=B_0x0, CKPOL=B_0x0, MCKOE=B_0x0, DATLEN=B_0x0, I2SSTD=B_0x0, WSINV=B_0x0, CHLEN=B_0x0, PCMSYNC=B_0x0
SPI/I2S configuration register
| I2SMOD | I2S mode selection 0 (B_0x0): SPI mode is selected 1 (B_0x1): I2S/PCM mode is selected |
| I2SCFG | I2S configuration mode 0 (B_0x0): slave - transmit 1 (B_0x1): slave - receive 2 (B_0x2): master - transmit 3 (B_0x3): master - receive 4 (B_0x4): slave - Full Duplex 5 (B_0x5): master - Full Duplex |
| I2SSTD | Iless thansup>2less than/sup>S standard selection 0 (B_0x0): Iless thansup>2less than/sup>S Philips standard. 1 (B_0x1): MSB justified standard (left justified) 2 (B_0x2): LSB justified standard (right justified) 3 (B_0x3): PCM standard |
| PCMSYNC | PCM frame synchronization 0 (B_0x0): short frame synchronization 1 (B_0x1): long frame synchronization |
| DATLEN | data length to be transferred. Data width of 24 and 32 bits are not always supported, (DATLEN = 01 or 10), refer to Section 58.3: SPI implementation to check the supported data size. 0 (B_0x0): 16-bit data length 1 (B_0x1): 24-bit data length 2 (B_0x2): 32-bit data length 3 (B_0x3): Not allowed |
| CHLEN | channel length (number of bits per audio channel) 0 (B_0x0): 16-bit wide 1 (B_0x1): 32-bit wide |
| CKPOL | serial audio clock polarity 0 (B_0x0): the signals generated by the SPI/I2S (i.e. SDO and WS) are changed on the falling edge of CK and the signals received by the SPI/I2S (i.e. SDI and WS) are read of the rising edge of CK. 1 (B_0x1): the signals generated by the SPI/I2S (i.e. SDO and WS) are changed on the rising edge of CK and the signals received by the SPI/I2S (i.e. SDI and WS) are read of the falling edge of CK. |
| FIXCH | fixed channel length in slave 0 (B_0x0): the channel length in Slave mode is different from 16 or 32 bits (CHLEN must be set) 1 (B_0x1): the channel length in Slave mode is supposed to be 16 or 32 bits (according to CHLEN) |
| WSINV | word select inversion 0 (B_0x0): In I2S Philips standard, the left channel transfer starts one CK cycle after the WS falling edge, and the right channel one CK cycle after the WS rising edge. 1 (B_0x1): In I2S Philips standard, the left channel transfer starts one CK cycle after the WS rising edge, and the right channel one CK cycle after the WS falling edge. |
| DATFMT | data format 0 (B_0x0): The data inside the SPI_RXDR or SPI_TXDR are right aligned 1 (B_0x1): The data inside the SPI_RXDR or SPI_TXDR are left aligned. |
| I2SDIV | Iless thansup>2less than/sup>S linear prescaler |
| ODD | odd factor for the prescaler 0 (B_0x0): Real divider value is = I2SDIV *2 1 (B_0x1): Real divider value is = (I2SDIV * 2) + 1 |
| MCKOE | master clock output enable 0 (B_0x0): Master clock output is disabled 1 (B_0x1): Master clock output is enabled |