CM55CACHEL=B_0x0, CM55L=B_0x0, CM55TCML=B_0x0, BKPRAML=B_0x0, PVDL_LOCK=B_0x0
SYSCFG control timer break register
| CM55L | CM55 lockup lock enable 0 (B_0x0): Cortex-M55 lockup output disconnected from TIM1/8/15/16/17 break inputs 1 (B_0x1): Cortex-M55 lockup output disconnected from TIM1/8/15/16/17 break inputs |
| PVDL_LOCK | PVD lock enable 0 (B_0x0): PVD interrupt disconnected from TIM1/8/15/16/17 break input. PVDE bits can be programmed by the application. 1 (B_0x1): PVD interrupt connected to TIM1/8/15/16/17 break input. PVDE and bits are read only. |
| BKPRAML | Backup SRAM double ECC error lock 0 (B_0x0): Backup SRAM double ECC error signal disconnected from TIM1/8/15/16/17 break inputs 1 (B_0x1): Backup SRAM double ECC error signal connected to TIM1/8/15/16/17 break inputs |
| CM55CACHEL | CM55 cache double ECC error lock 0 (B_0x0): Cortex-M55 cache double ECC error signal disconnected from TIM1/8/15/16/17 break inputs 1 (B_0x1): Cortex-M55 cache double ECC error signal connected to TIM1/8/15/16/17 break inputs |
| CM55TCML | CM55 TCM double ECC error lock 0 (B_0x0): Cortex-M55 TCM double ECC error signal disconnected from TIM1/8/15/16/17 break inputs 1 (B_0x1): Cortex-M55 TCM double ECC error signal connected to TIM1/8/15/16/17 break inputs |